1. Field of the Invention
This invention generally relates to a signal processing circuit of a one-dimensional image sensor and in particular to a signal preprocessing circuit of a line sensor for use in a facsimile machine or the like.
2. Description of the Prior Art
As an image sensor for use in a facsimile or the like, use has been made of a contact-type line sensor comprised of CCD or MOSFET elements and brought into contact with an original for optical reading thereof. An image signal obtained by electronically scanning such a contact-type line sensor is different in nature from that obtained by mechanical scanning using a single sensor. In particular, in the case of a contact-type line sensor, low frequency distortions tend to be introduced. This is because it is difficult to apply irradiation along the entire line uniformly and also it is difficult to manufacture a line sensor having a plurality of photoelectric elements all uniform in characteristic and thus same in sensitivity. Such distortions may originate from various factors, such as shading, non-uniformity in characteristic among photoelectric elements, a reduction of MTF (Modulation Transfer Function) and fluctuations of a peak value.
These distortions could have adverse effects on outputting image information of an original in the form of a binary value signal or a multi-value signal. Thus, it is required to provide a preprocessing circuit for correcting such distortions to thereby improve the stability and accuracy of an image signal obtained by optically reading an original. In addition, in the case of applications to facsimile machines, in order to optically read the information written on originals having different background levels, it is necessary to vary the dynamic range of a preprocessing circuit following the variation of a peak value which represents the maximum value (white) of the background level of an original.
Typical prior art preprocessing circuits of a line sensor are shown in FIGS. 2 and 5. In a preprocessing circuit shown in FIG. 2, when a shading waveform is input into a peak detecting circuit 50, a peak value V.sub.p0 is detected as shown in FIG. 3, which is then input into the reference input terminal of a successive A/D converter 52. At the successive A/D converter 52, the shading waveform is converted into a digital signal which is then stored in a RAM 54. Then, when an image signal is input next, its peak value V.sub.p1 is similarly detected, which is then input into the reference input terminal of the successive A/D converter 52. At the same time, the contents of the RAM 52 are read out and the successive A/D converter 52 is operated as a D/A converter to thereby reproduce an analog shading signal V.sub.s as shown in FIG. 4. By utilizing a dividing function provided between the reference and input voltage inputs of the successive A/D converter 52, the thus reproduced shading signal V.sub.s is proportional to the peak value V.sub.p1. With V.sub.s input as the reference voltage of a parallel A/D converter 56, the image signal is subjected to A/D conversion. In this manner, there is provided a preprocessing circuit which can follow the fluctuations of shading and peak value.
The preprocessing circuit shown in FIG. 2 is typically constructed in the form of LSI. However, it is to be noted that the preprocessing circuit shown in FIG. 2 requires the provision of two A/D converters, which is disadvantageous.
FIG. 5 illustrates another prior art preprocessing circuit which is also typically constructed in the form of LSI. In this preprocessing circuit, shading is digitized by a parallel A/D converter 58 and the data converted by a ROM 60 is stored in a RAM 62. Then, when an image signal has been input, in synchronism with the process of converting it into digital data by the parallel A/D converter 58, the contents of the RAM 62 are read out and thus a corrected 6-bit digital image signal is output from a digital multiplier 64. This preprocessing circuit also includes a controller 66 and a selector 68. It is to be noted, however, that the preprocessing circuit shown in FIG. 5 requires the provision of the digital multiplier 64 and the ROM 60, which is also disadvantageous.